This invention relates to a branch instruction processing unit capable of executing branch-on-count instructions for controlling loops in a program.
In a program for scientific and technical computation such as DO loops of a FORTRAN program, the same processing is often repeated for a limited number of times. In this case, branch-on-count instructions (referred to as "BCT instructions" hereinafter) are frequently used as branch instructions. With a BCT instruction, the content of a designated register is read out, subtracted by "1" and then stored again in the original register. If the result of subtraction is "0", it is judged that the branching has not been successful, while if that result is other than "0", it is judged that the branching has been successful. Such a BCT instruction is placed at the end of a group of instructions to be looped and the location to be branched is indicated by the address of the topmost instruction of the group. After the number of looping times is loaded in a specific register, the instructions of the group are consecutively executed from the topmost instruction, and this group of the instructions is repeated a specific number of times.
In the prior art, two processing steps are taken serially to execute the BCT instruction; i.e.,
(1) the step of subtracting "1" from a specific register, PA1 (2) the step of judging whether or not branching is taken based on the result of subtraction.
Since a conventional branch instruction processing unit must execute the processing step (2) after the execution of the processing step (1), each BCT instruction inconveniently takes longer time for execution than other branch instructions which do not need the subtraction process mentioned above (1).
In order to overcome this problem, there has been proposed a technique by Hitachi, Ltd. in the Japanese Pat. Publication No. 20385/1979. According to the proposed technique, a display register is provided corresponding to a general purpose register which stores the number of loop times in order to display whether the content of the register is "1" or not. In response to "1" written in the general purpose register, the display register is set. Prior to the execution of a BCT instruction, the content of the display register is read out and whether or not the branching is successful is judged depending on the read-out content.
This technique enables immediate judgement on whether or not the branching is to be taken depending on the content of the display register at the initiation of the execution of each BCT instruction and, therefore, can enhance the speed of execution. However, if a plurality of general purpose (GP) registers for storing the number of loop times are used to process a BCT instruction, a corresponding number of display registers must be employed for detecting which GP register is being used for the BCT instruction, thereby increasing the amount of hardware undesirably.